Electrical overstress (EOS) and electrostatic discharge (ESD) are reliability problems which can lead to the damage of sensitive integrated circuit components. An ungrounded conductive object or person can accumulate static electric charges by induction or by contact with charged insulators. If the object or person then comes in contact with an integrated circuit and is discharged through a path which is electrically connected to elements sensitive to the ESD transient, large currents will be generated which can damage those elements. In an integrated circuit, this damage typically occurs to the thin oxide layers and shallow junctions of the component transistors.
Owing to the sensitivity of the internal circuit elements which are part of an integrated circuit chip to damage arising from ESD, input/output devices connected to these elements are designed to be very robust, i.e., capable of handling large ESD transients without creating a conducting path to the circuit elements. Interface cable drivers are a specific example of I/O circuitry which require enhanced robustness and the ability to shield more sensitive internal circuit elements to which they are connected from damage. Interface cable drivers are electrically connected right behind the peripheral ports and connectors of many products and the protection circuitry associated with the drivers provides the first line of defense from EOS and ESD for the internal circuitry.
FIG. 1 is a schematic diagram of a conventional NMOS based I/O protection circuit 20 for preventing damage to the attached internal circuitry from EOS. As shown in the figure, protection circuit 20 is electrically positioned between I/O pad 22 and the internal circuitry to be protected from EOS. If Vx produced by an ESD signal applied to I/O pad 22 is much larger than V.sub.DD for NMOS transistor T1 24, then transistor 24 turns on due to punchthrough and Vx is clamped. This prevents the transient signal applied to I/O pad 22 from exceeding a value above which the internal circuitry would be damaged. If Vx is one threshold voltage level below ground, transistor 24 turns on naturally and the value of Vx applied to the internal circuitry is again limited (clamped) because a conducting path to ground is provided. Resistor 26 serves to protect transistor 24 by limiting the current and power flowing through the protection circuit.
In protection circuit 20 of FIG. 1, transistor 24 is configured to act as a diode, turning on and shunting the transient signal applied to I/O pad 22 to ground and away from the internal circuitry when the transient signal exceeds a desired level. This is the basic concept behind most protection circuits; at a predetermined level, a circuit element switches on and provides a conducting path for the signal to ground and away from the sensitive circuit elements. However, such diode (or equivalently, transistor configured to operate as a diode) based circuits have an inherent limitation. If the internal circuitry on the integrated circuit chip to which the protection circuit is connected is designed to operate at voltages above the diode breakdown voltage (or transistor punchthrough, etc.), then such a protection circuit will prevent the required voltage from reaching the circuitry. One solution is to design a diode (or transistor) with a higher breakdown voltage. However, this may require a redesign of the process flow used to construct the diode and internal circuitry. This is an expensive and inefficient solution to the problem.
FIGS. 2A-B are schematic diagrams of an improved version of the conventional NMOS based I/O protection circuit of FIG. 1. In FIG. 2A, diode D1 30 is connected between ground and the gate of transistor 24. The diode is used to prevent the breakdown of the thin gate oxide of transistor 24. Tying the gate of transistor 24 to ground through diode 30 can serve to reduce the EOS on the protection circuit. This is because during normal operation (i.e., Vx between zero and V.sub.DD), the gate of transistor 24 is floating and the transistor is off. When the input transient signal exceeds the allowed range, transistor 24 turns on. At this time, some of the voltage swing is capacitively coupled from node A to node B. As a result, the thin gate oxide of transistor 24 is not stressed as much as it would be in the absence of diode 30. When diode 30 is turned on, the charge at the gate capacitance of transistor 24 is discharged and the input signal is clamped. FIG. 2B shows the same protection circuit as FIG. 2A with the exception that a properly configured transistor 32 (labelled "T2" in the figure) is used instead of diode 30. The circuits of FIGS. 2A-B act to shunt the transient signal to ground faster than the circuit of FIG. 1 by capacitively coupling the transient signal onto the gate of transistor 24, thereby turning on diode 30 or transistor 32 sooner.
FIG. 3 is a schematic diagram of a two-stage protection circuit which can be used to protect internal circuit elements from electrical overstress. In FIG. 3, a floating N well 40 is placed beneath pad 22 to prevent the pad metal from spiking into the substrate. Floating well 40 acts as a reverse-biased diode and isolates the metal from the substrate. Field oxide transistor (FOT) 42 and n-well enhanced diode 44 form the first stage of the protection circuit. FOT 42 has a large threshold potential, but is immune to the effects of EOS and ESD. Diode 44 serves as the source/drain diffusion of FOT 42. As is typical in such FOT based protection circuits, the gate and drain of FOT 42 are shorted together and tied to the input signal, with the source and body of FOT 42 tied to ground (or Vss).
FOT 42 and diode 44 are robust devices which clamp the gross voltage and current spikes produced by the transient signal applied to I/O pad 22. Thus, both FOT 42 and diode 44 provide a low resistive shunting path for the transient, removing the gross voltage spikes from the signal Diodes 46 and 48 form the second stage of the protection circuit. They act to filter out the smaller amplitude spikes which are not removed by the first stage devices. The use of an FOT as part of a protection circuit has the benefit that the device turns on and shunts away the transient (i.e., clamps the applied signal) at higher voltages than the breakdown voltage for diodes typically used in protection circuits. This eliminates one problem of using diodes in such protection circuits because the turn-on voltage of the FOT is typically above that of the power supply range used to operate the internal circuitry.
Although the protection circuits of FIGS. 2 and 3 provide improved operation over that of FIG. 1, they also have certain limitations. The circuits of FIGS. 2A-B respond faster and act to shunt the transient away sooner than the circuit of FIG. 1. However, they can still cause clamping at a voltage level below that desired for proper operation of the internal circuitry. In addition, the protection circuits of FIGS. 2A-B are susceptible to accidental triggering during rapid power up or by noisy power supplies, thereby preventing proper operation of the connected circuitry. This means that the protection circuit must be disabled during the power up cycle, an inefficient and potentially hazardous step.
The protection circuit of FIG. 3 has the disadvantage that diode 44 and/or FOT 42 may not turn on quickly enough to prevent the transient signal from damaging the internal circuitry. When the FOT begins conducting, it acts to shunt away a lower amount of current than it does at the higher gate to source voltage achieved after the turn-on period. Thus, during the turn-on period, the transient may propagate along a conductive path and damage the internal circuitry in addition, diodes 46 and 48 will typically clamp the signal at a level below that required for operation of some types of internal circuitry.
FIG. 4 is a schematic diagram 100 of a prior art design of an interface cable driver (the elements in the box labelled 102) with associated EOS protection circuit (diode 104). The output of circuit 102 is differential, thus the figure shows only one of two identical outputs. Lower output transistor 106 and upper output transistor 108 are typically NMOS transistors. As shown in the figure, a parasitic bipolar diode is formed by the source and drain junctions of transistors 106 and 108. Data generated, or to be processed, by the internal circuitry propagates along connected data lines 112. Driver circuit 102 is used to amplify the data provided on data lines 112 prior to its being sent out of an I/O port along attached cable 111, which is the medium along which an ESD transient signal would propagate. Thus, diode 104 (or another protection circuit) provides the first line of EOS defense for both interface driver 102 and the internal circuitry attached to data lines 112.
Interface cable driver circuit 102 must be capable of operating properly under a range of test conditions appropriate to the intended use of the circuit. Driver circuit 102 is typically tested in both voltage output low (VOL) and voltage output high (VOH) conditions with the current being forced into and out of output pad 110. A device of the type shown in FIG. 4 is deemed satisfactory if it can withstand a given current amount or compliance voltage under all applicable test conditions. When a current transient is forced out of output 110 in a VOL condition, the diodes formed by the drain-well and source-well junctions of transistors 106 and 108 conduct up to their maximum current density capability. During a VOL condition, when current is forced into the device, transistor 106 is on and will conduct its maximum current density, thus shunting away any transient received along cable 111 prior to the breakdown of diode 104. When driver 102 is in a VOH condition and the current is forced out of the device, the diodes formed by the drain-well and source-well junctions of transistors 106 and 108 conduct up to their maximum current density capability. However, when the output is in a VOH condition and current is forced into the device it will "snapback" transistor 106, force transistor 106 into secondary snapback and eventually damage driver 102 before it can meet the compliance voltage. Diode 104 is used as an EOS protection device to shield driver 102 and the internal circuitry attached to data lines 112 from any excessively strong transient signal by shunting it to ground when the transient voltage exceeds the breakdown voltage of the diode. Other suitable protection elements may of course be used, such as a properly configured transistor. In all such configurations of the driver and protection element(s), the protection elements are used to both sense the excessive transient and to operate to shunt the transient away from the driver circuit and into ground.
The operation of interface driver circuit 102 will now be explained in greater detail. Assume that the data value is a one. Then data-bar has a value of zero. The output of inverter 1 107 (labelled "inv1" in the figure) is a zero. The output of inverter 2 105 (labelled "inv2" in the figure) is a one. This means that transistor 108 is "off" and transistor 106 is "on". In such a situation, when a strong ESD transient is applied through the connection to cable 111, the breakdown of diode 104 produces a conducting path to ground labelled "Vss" in the figure) for the transient. In addition, the normal operation of transistor 106 provides a conducting path for any portion of the transient not shunted by diode 104.
Now consider the situation where the data value is a zero. Then data-bar has a value of one. The output of inverter 1 107 (labelled "inv1" in the figure) is a one. The output of inverter 2 105 (labelled "inv2" in the figure) is a zero. This means that transistor 108 is "on" and transistor 106 is "off". Now when a strong ESD transient is applied through the connection to cable 111, a problem can occur. With transistor 106 off and transistor 108 on, a conducting path is supplied through transistor 108 to the power supply (labelled "Vdd" in the figure). The transient can harm the power supply components, damage inverter 1 107, and possibly damage the internal circuitry connected to data lines 112.
While all of the ESD protection circuits described are capable of providing some degree of protection for the interface driver and/or internal circuitry, they all have disadvantages. These disadvantages become important when the operating voltage of the internal circuitry is above that of the breakdown voltage of the diode (or properly configured transistor) used to protect the circuitry. They also become important when the turn-on time or breakdown time of the protection circuit isn't fast enough to prevent a transient signal from either bypassing or propagating through the protection circuit to the sensitive internal circuitry.
What is desired is a circuit which provides EOS and ESD protection for an interface cable driver and other internal circuitry connected to the driver which overcomes the noted disadvantages of the art. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the Detailed Description of the Invention together with the drawings.